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products:w7100a:sfr_definition

SFR definition

The following section describes SFR of W7100A and its functions.
For more detailed information about peripheral SFR, please refer to the section Peripheral-SFR.

Overview:

SFR Memory Map

All of the SFR in the left hand side column ending with 0 or 8 are bit addressable.

from 0 / 8 1 / 9 2 / A 3 / B 4 / C 5 / D 6 / E 7 / F to
0xF8 EIP DPSBK RAMBA16 RAMEA16 PHYCONF WCONF 0xFF
0xF0 B ISPID ISPADDR16 ISPDATA CKCBK DPX0BK DPX1BK 0xF7
0xE8 EIE MXAX P0_PU P1_PU P2_PU P3_PU PHY_IND 0xEF
0xE0 ACC P0_PD P1_PD P2_PD P3_PD 0xE7
0xD8 WDCON CLK_CNTx 0xDF
0xD0 PSW 0xD7
0xC8 T2CON RLDL RLDH TL2 TH2 0xCF
0xC0 Res. TA 0xC7
0xB8 IP 0xBF
0xB0 P3 0xB7
0xA8 IE 0xAF
0xA0 P2 0xA7
0x98 SCON0 SBUF INTWTST EXTWTST ALECON 0x9F
0x90 P1 EIF WTST DPX0 DPX1 0x97
0x88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 0x8F
0x80 P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON 0x87


New SFR – New additional SFR, described in this section

Peripheral SFR, described in this section

Extended SFR – Extended from standard 8051, described in this section

Standard – standard 8051 SFR, described in this section

2013/11/13 00:09 · Joachim Wuelbeck

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Program Code Memory Write Enable Bit

Inside the PCON register, the Program Write Enable (PWE) bit is used to enable/disable Program Write signal activity during MOVX instructions. When the PWE bit is set to logic ‗1', the ―MOVX @DPTR, A‖ instruction writes the data from the accumulator register into the code memory addressed by using the DPTR register (active DPH:DPL) The ―MOVX @Rx, A‖ instruction writes the data from the accumulator register into code memory addressed by using the P2 register (bits 15:8) and Rx register (bits 7:0).

PCON (0x87) - link - ..

products/w7100a/sfr_definition.txt · Last modified: 2015/03/16 10:33 (external edit)