W7500P embeds a voltage regulator in order to supply the internal 1.5V digital power domain.
The voltage regulator is always enabled after Reset and works on in only one mode.
The power-up time reference voltage is 2.7V.
Symbol | Parameter | Conditions | Min | Max | Unit |
---|---|---|---|---|---|
TVDD | VDD rise time | 0 | 20 | ms |
W7500P is in RUN mode after a system or power reset. There are two low power modes to save power when the CPU does not need to be kept running. These modes are useful for instances like when the CPU is waiting for an external interrupt. Please note that there is no power-off mode for W7500P.
The device features two low power modes:
Additionally, the power consumption can be reducing by following method:
W7500P has two kinds of sleep modes. One is Sleep mode and the other is Deep sleep mode. Two of them are almost the same except the clock gated peripherals kinds.
Mode | Entry | Wakeup | Effect-on-clocks |
---|---|---|---|
Sleep mode | DEEPSLEEP = 0 Enable WFI |
Any interrupt | CPU Clock OFF APB Bus Clock ON AHB Bus Clock ON Memory Clock ON |
DEEPSLEEP = 0 Enable WFE |
Wakeup event | ||
Deep Sleep mode | DEEPSLEEP = 1 Enable WFI |
Any interrupt | CPU Clock OFF APB Bus Clock OFF AHB Bus Clock OFF Memory Clock OFF |
DEEPSLEEP = 1 Enable WFE |
Wakeup event |
In Run mode, individual clocks can be stopped at any time to reduce power. Peripheral clock gating is controlled by the CRG block. Below is the list of clocks which can be gating in CRG block.