CRG is clock reset generator block for W7500P System. It provides every clock/reset for all other block include CPU and peripherals. CRG includes PLL and POR.
Two clock sources can be used to drive the system clock.
One additional clock source
There is a PLL One PLL is integrated
There are many generated clocks for independent operating with system clock
RNGCLK have only one source (pll output) and no prescaler Some of the generated clocks turn off automatically when CPU enters sleep mode.
Generate two Hardware TCPIP Clocks (MII_RXC, MII_TXC) are from external PADs.
Hardware TCPIP Clocks can be gated by register control.
All clocks generated from CRG can be monitored.
External oscillator clock (OCLK) can be generated from two possible clock source
RC oscillator clock (RCLK) signal is generated from an internal 8MHz RC oscillator.
RC oscillator has the advantage of providing a clock source at low cost (no external components).
However accuracy of RC oscillator is less than external crystal or ceramic resonator.
The internal PLL can be used to multiply the External Oscillator Clock (OCLK) or RC Oscillator Clock (RCLK). PLL input can be selected by register. PLL output clock can be generated by following the equations below.
Each generated clock source can be selected among 3 clock source as independent by each clock source select register
Each generated clock has own prescaler which can be select individually by each prescale value register