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"Connect the Magic" Resources

Connect the Magic design challenge launches on March 3, 2014 and commences on August 3, 2014. The challenge is straightforward. Implement WIZnet’s WIZ550io Ethernet module, or W5500 chip, in an innovative design, document your project, and submit your entry.

How to Win

Challenge Entries that meet the Challenge’s submission requirements and comply with the rules will be judged by a panel of judges selected by the Administrator and Sponsor on the following: technical merit 30%, originality 30%, usefulness 20%, cost-effectiveness 10%, and design optimization 10%.

Prize

The following Challenge prizes will be awarded:

  • $5,000 First Prize
  • $3,000 Second Prize
  • $2,000 Third Prize
  • Five (5) Honorable Mention prizes of $1,000 each.

Sample Request & Registration

Primer Article

Forum for technical support

W5500

W5500 The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface). W5500 suits users in need of stable internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY.

W5500 Datasheet

Datasheet

Datasheet History
Version Date Description
1.0.0 2013-08-01 Initial Release
1.0.1 2013-09-13 Corrected duplicated statements and typing errors (P.14, 23, 24, 28, 39, 51) Corrected descriptions (P.35)
1.0.2 2013-11-14 Changed “descriptions of pin at 1.1 Pin Descriptions” (P.10) starting ”It must be tied to GND to NC (PIN38..42)” / 2. corrected typing error: starting “0x02 to 0x42 value of SOCK_MACRAW at 4.2 Socket Registers(P.50)”
1.0.3 2014-05-29 Corrected “Sn_MSSR at 4.2 Socket Register” (P.53): wrong descriptions of Sn_MSSR about FMTU/MTU
1.0.4 2014-06-13 1. Added Note about reading size register value (P.56, 58) / 2. Added IR Reflow Temperature Profile (P.66)
1.0.5 2014-11-11 1. Added description for MISO pin (P.11):The SCSn signal defines MISO pin output value / 2. Modified the register notation (P.33), Modified the register notation “Sn_IR at 4.2 Socket Register” (P.49) :from [R] to [RCW1] / 3. Corrected typing error: from DICON to DISCON of Sn_SR at 4.2 Socket Register (P.50)
1.0.6 2014-12-30 Corrected typing error : from 0x02 to 0x42 value of SOCK_MACRAW “Sn_CR at 4.2 Socket Registers”(P.46)
1.0.7 2016-02-24 1. Corrected Interrupt Assert Wait Time function (P.34) / 2. Notice PLLclk is 150MHz (P.34)

WIZ550io History
Version Date Description
1.0 2013-08-01 Initial Release
1.1 2014-01-17 Changed “External Transformer + RJ-45 to MAGJACK(inside transformer)”
1.2 2015-04-20 Added “Resistor 33R in MDI line. because EMI issue.”
Changed “PCB artwork. because changed develop tool(PADS → Altium) ”

2013/08/30 10:01 · bongbong

W5500 Driver Code

WIZ550io

WIZ550io is an auto configurable Ethernet controller module that includes W5500 (TCP/IP hardwired chip and PHY embedded), transformer and RJ45.

It has a unique real MAC address and configures the network setting automatically. When just powered on, WIZ550io initializes itself with embedded real MAC and set the default IP address(192.168.1.2) and can be pinged. So, user doesn’t need to write MAC and network information like IP address, Subnet mask and Gateway address.

The WIZ550io is an ideal product for users who want to develop their Internet enabling systems rapidly.
For more information about W5500 inside WIZ550io, refer to the W5500 Datasheet page.

Pinout

Block Diagram

Schematic

BOM

2014/02/07 15:38 · peter.kim

Dimension

WIZ550io Ver1.1

Open Source Hardware Example

WIZ550io allows ethernet connectivity for many OSHW platform using 'ioShields'. In addition, WIZnet provides driver and example application source code for various platforms.

connectthemagic.txt · Last modified: 2015/03/16 10:33 (external edit)