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products:w7500:overview:systemandmemory [2015/04/27 19:31]
leo
products:w7500:overview:systemandmemory [2015/05/12 08:54] (current)
lawrence
Line 19: Line 19:
 AHB-Lite BUS AHB-Lite BUS
  
-- This bus connects two masters (Cortex-M0 and uDMAC) and ten AHB slaves.+- This bus connects ​the two masters (Cortex-M0 and uDMAC) and ten AHB slaves.
  
 Two APB BUSs Two APB BUSs
  
-- These buses connect ​seventeen ​APB peripherals (Watchdog, two dual timers, pwm, two UARTs, simple UART, two I2Cs, two SSPs, random number generator, real time clock, 12bits analog digital converter, clock controller, IO configuration,​ PAD MUX controller)+- These buses connect ​Seventeen ​APB peripherals (Watchdog, two dual timers, pwm, two UARTs, simple UART, two I2Cs, two SSPs, random number generator, real time clock, 12bits analog digital converter, clock controller, IO configuration,​ PAD MUX controller)
  
  
 ## Memory organization ## Memory organization
  
-Program memory, data memory, registers and I/O ports are organized within the same linear ​4Gbyte ​address space. +Program memory, data memory, registers and I/O ports are organized within the same linear ​4-Gbyte ​address space. 
-The bytes are in little endian ​format. ​byte out of a word in the lowest address ​is considered the word’s least significant byte and the highest ​address ​byte is the most significant.+The bytes are coded in memory in Little Endian ​format. ​The lowest numbered ​byte in a word is considered the word’s least significant byte and the highest ​numbered ​byte the most significant.
  
 ###Memory map ###Memory map
products/w7500/overview/systemandmemory.1430130700.txt.gz · Last modified: 2015/04/27 19:31 by leo