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products:w7500:overview:systemandmemory [2015/04/27 13:26]
justinkim
products:w7500:overview:systemandmemory [2015/05/12 08:54] (current)
lawrence
Line 6: Line 6:
   * Two masters:   * Two masters:
     * Cortex-M0 core     * Cortex-M0 core
-    * uDMAC(PL230, ​60channel)+    * uDMAC(PL230, ​6 channels)
   * Ten slaves   * Ten slaves
     * Internal BOOT ROM     * Internal BOOT ROM
Line 13: Line 13:
     * Two AHB2APB bridge which connects all APB peripherals     * Two AHB2APB bridge which connects all APB peripherals
     * Four AHB dedicated to 16-bit GPIOs     * Four AHB dedicated to 16-bit GPIOs
-    * TCPIP Hardware core+    * TCP/​IP ​Hardware core
  
 ![](http://​wizwiki.net/​wiki/​lib/​exe/​fetch.php?​media=products:​w7500:​overview:​w7500_system_architecture.png "W7500 System Architecture"​) ![](http://​wizwiki.net/​wiki/​lib/​exe/​fetch.php?​media=products:​w7500:​overview:​w7500_system_architecture.png "W7500 System Architecture"​)
products/w7500/overview/systemandmemory.1430108801.txt.gz ยท Last modified: 2015/04/27 13:26 by justinkim